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Freescale Semiconductor Advance Information
Document Number: MC33874
Rev. 8.0, 4/2007
Quad High-Side Switch (Quad 35 m)
The 33874 is one in a family of devices designed for low-voltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (four 35 m) can control the high sides of four separate resistive or inductive loads. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for pulse-width modulation (PWM) control if desired. The 33874 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33874 is packaged in a power-enhanced 12 x 12 nonleaded Power QFN package with exposed tabs. Features * Quad 35 m High-Side Switches (at 25C) * Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 A * SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output OFF Open Load Detection, Output ON / OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting * SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status * Analog Current Feedback with Selectable Ratio * Analog Board Temperature Feedback * Enhanced -16 V Reverse Polarity VPWR Protection * Pb-Free Packaging Designated by Suffix Code PNA
VDD VDD VPWR VDD
33874
HIGH-SIDE SWITCH
PNA SUFFIX (PB_FREE) 98ARL10596D 24-PIN PQFN (12 x 12)
ORDERING INFORMATION
Device MC33874BPNA/R2 Temperature Range (TA) - 40C to 125C Package 24 PQFN
VPWR
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VDD WAKE SO SCLK CS SI MCU I/O I/O I/O I/O I/O I/O A/D GND A/D SI SCLK CS SO RST FS IN0 IN1 IN2 IN3 CSNS TEMP FSI GND HS3 LOAD 3 HS2 LOAD 2 HS1 LOAD 1 VPWR HS0 LOAD 0
Figure 1. 33874 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD VPWR
VIC
IUP CS SCLK IDWN SO SI RST WAKE FS IN0 IN1 IN2 IN3
SPI 3.0 MHz
Internal Regulator
Over/Undervoltage Protection
VIC
Selectable Slew Rate Gate Drive Selectable Overcurrent High Detection HS[0:3]: 55 A or 40 A Selectable Overcurrent Low Detection Blanking Time 0.15 ms-155 ms Open Load Detection Overtemperature Detection Selectable Overcurrent Low Detection HS[0:3]: 2.8 A-10 A
HS0
Logic
HS0
RDWN
IDWN HS1
HS1
Programmable Watchdog 279 ms-2250 ms
VIC
HS2 HS2
FSI HS3 HS3
Temperature Feedback Selectable Output Current Recopy (Analog MUX) HS[0:3]: 1/7200 or 1/21400
TEMP
GND
CSNS
Figure 2. 33874 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
Transparent Top View of Package
WAKE TEMP CSNS 1 24 14 GND 23 FSI GND 22 HS2 Definition The Current Sense pin sources a current proportional to the designated HS0 : HS3 output. The IN0 : IN3 high-side input pins are used to directly control HS0 : HS3 highside output pins, respectively. SCLK VDD
RST
IN3
IN2
IN1 3
13 12 11 10 SO GND 16 17
9
8
7
6
5
4
HS3
18
15 VPWR
19 HS1
20 NC
21 HS0
Figure 3. 33874 Pin Connections Table 1. 33874 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number 1 2 3 5 6 4 7 8 9 10 11 12 13 Pin Name CSNS IN0 IN1 IN2 IN3 TEMP FS WAKE RST CS SCLK SI VDD Pin Function Output Input Formal Name Output Current Monitoring Serial Inputs
Output Output Input Input Input Input Input Power
Temperature Feedback Fault Status (Active Low) Wake Reset Chip Select (Active Low) Serial Clock Serial Input Digital Drain Voltage (Power)
This pin reports an analog value proportional to the temperature of the GND flag (pins 14, 17, 23). It is used by the MCU to monitor board temperature. This pin is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. This input pin controls the device mode and watchdog timeout feature if enabled. This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low-current sleep mode. This input pin is connected to a chip select output of a master microcontroller (MCU). This input pin is connected to the MCU providing the required bit shift clock for SPI communication. This pin is a command data input pin connected to the SPI Serial Data Output of the MCU or to the SO pin of the previous device of a daisy-chain of devices. This pin is an external voltage input pin used to supply power to the SPI circuit.
IN0 2
CS
FS
SI
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PIN CONNECTIONS
Table 1. 33874 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number 14, 17, 23 15 16 18 19 21 22 20 24 Pin Name GND VPWR SO HS3 HS1 HS0 HS2 NC FSI Pin Function Ground Power Output Output Formal Name Ground Definition These pins are the ground for the logic and analog circuitry of the device.
Positive Power Supply This pin connects to the positive power supply and is the source of operational power for the device. Serial Output High-Side Outputs This output pin is connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device of a daisy-chain of devices. Protected 35 m high-side power output pins to the load.
N/A Input
No Connect Fail-Safe Input
This pin may not be connected. The value of the resistance connected between this pin and ground determines the state of the outputs after a Watchdog timeout occurs.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Operating Voltage Range Steady-State VDD Supply Voltage Input / Output Voltage (1) SO Output Voltage
(1)
Symbol
Value
Unit
VPWR(SS) -16 to 41 VDD
See note (1)
V -0.3 to 5.5 - 0.3 to 7.0 - 0.3 to VDD + 0.3 2.5 10 41 -16 V V V mA mA V
VSO ICL(WAKE) ICL(CSNS) VHS
WAKE Input Clamp Current CSNS Input Clamp Current HS [0:3] Voltage Positive Negative Output Current (2) Output Clamp Energy ESD Voltage (4) Human Body Model (HBM) Charge Device Model (CDM) Corner Pins (1, 13, 19, 21) All Other Pins (2-12, 14-18, 20, 22-24) THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance (5) Junction to Case Junction to Ambient Peak Pin Reflow Temperature During Solder Mounting (6)
(3)
IHS[0:3] ECL [0:3] VESD
11 85 2000 750 500
A mJ V
C
TA TJ TSTG RJC RJA TSOLDER - 40 to 125 - 40 to 150 - 55 to 150 <1.0 30 240
C C/ W
C
Notes 1. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, TEMP, SI, SO, SCLK, CS, or FS pins may cause a malfunction or permanent damage to the device. 2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. Active clamp energy using single-pulse method (L = 2 mH, RL = 0 , VPWR = 14 V, TJ = 150C initial). 4. 5. 6. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). Device mounted on a 2s2p test board per JEDEC JESD51-2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER INPUT (VPWR, VDD) Battery Supply Voltage Range Fully Operational VPWR Operating Supply Current Outputs ON, HS[0 : 3] open VPWR Supply Current Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 VDD, RST = VLOGIC HIGH Sleep State Supply Current (VPWR = 14V, RST < 0.5 V, WAKE < 0.5 V) TA = 25C TA = 85C VDD Supply Voltage VDD Supply Current No SPI Communication 3.0 MHz SPI Communication (7) VDD Sleep State Current Overvoltage Shutdown Threshold Overvoltage Shutdown Hysteresis Undervoltage Shutdown Threshold (8) Undervoltage Hysteresis
(9)
Symbol
Min
Typ
Max
Unit
VPWR 6.0 IPWR(ON) - IPWR(SBY) - IPWR(SLEEP) - - VDD(ON) IDD(ON) - - IDDSLEEP VOV VOVHYS VUV VUVHYS VUVPOR - 28 0.2 4.75 - - - - - 32 0.8 5.25 0.25 - 1.0 5.0 5.0 36 1.5 5.75 - 4.75 4.5 1.0 - 5.0 10 50 5.5 - 5.0 - 20 - 27
V mA mA
A
V mA
A V V V V V
Undervoltage Power-ON Reset
Notes 7. Not guaranteed in production. 8. The undervoltage fault condition is reported to SPI register as long as the external VDD supply is within specification and the VPWR voltage level does not go below the undervoltage Power-ON Reset threshold. 9. This applies when the undervoltage fault is not latched (IN = [0:3]).
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic OUTPUTS (HS0, HS1, HS2, HS3) Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 25C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Drain-to-Source ON Resistance (IHS = 5.0 A, TA = 150C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V Output Source-to-Drain ON Resistance
(10)
Symbol
Min
Typ
Max
Unit
RDS(ON) - - - RDS(ON) - - - RSD(ON) - IOCH0 IOCH1 IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 CSR0 CSR1 CSR0_ACC -17 - 17 44 32 8.0 7.1 6.3 5.6 4.6 3.8 3.1 2.2 - - - 55 40 10 8.9 7.9 7.0 5.8 4.8 3.9 2.8 1/7200 1/21400 70 - - - 94 60 60 - - - 55 35 35
m
m
m A 66 48 A 12 10.7 9.5 8.5 7.0 5.8 4.7 3.4 - - - %
IHS = 1.0 A, TA = 25C, VPWR = -12 V Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 Overcurrent Low Detection Levels (9.0 V < VPWR < 16 V) SOCL[2:0] : 000 SOCL[2:0] : 001 SOCL[2:0] : 010 SOCL[2:0] : 011 SOCL[2:0] : 100 SOCL[2:0] : 101 SOCL[2:0] : 110 SOCL[2:0] : 111 Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 Current Sense Ratio (CSR0) Accuracy Output Current 2.0 A to 10 A
Notes 10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic OUTPUTS (HS0, HS1, HS2, HS3) (continued) Current Sense Ratio (CSR1) Accuracy Output Current 10 A to 20 A Current Sense Clamp Voltage CSNS Open; IHS[0:3] = 11 A Open Load Detection Current (11) Output Fault Detection Threshold Output Programmed OFF Output Negative Clamp Voltage 0.5 A < IHS[0:3] < 2.0 A, Output OFF Overtemperature Shutdown (12) Overtemperature Shutdown Hysteresis
(12)
Symbol
Min
Typ
Max
Unit
CSR1_ACC -19 VCL(CSNS) 4.5 IOLDC VOFD(THRES) 2.0 VCL - 20 TSD TSD(HYS) 155 5.0 - 175 - -16 190 20 3.0 4.0 30 6.0 - 7.0 100 - 19
%
V A V V
C C
Notes 11. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 12. Guaranteed by process monitoring. Not production tested.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic CONTROL INTERFACE (SCLK, SI, SO, IN[0:3], RST, WAKE, FS, CS, FSI) Input Logic High Voltage (13) Input Logic Low Voltage (13) Input Logic Voltage Hysteresis
(14)
Symbol
Min
Typ
Max
Unit
VIH VIL VIN(HYS) IDWN VRST CSO RDWN
0.7 VDD - 100 5.0 4.5 - 100 - 7.0
- - 850 - 5.0 - 200 4.0 - - - 0.2 0 -
- 0.2 VDD 1200 20 5.5 20 400 12 14
V V mV A V pF k pF V V
Input Logic Pulldown Current (SCLK, SI, IN[0:3], VIN>0.2 VDD)
RST Input Voltage Range
SO, FS Tri-State Capacitance (14) Input Logic Pulldown Resistor (RST) and WAKE Input Capacitance (15) Wake Input Clamp Voltage ICL(WAKE) < 2.5 mA Wake Input Forward Voltage ICL(WAKE) = -2.5 mA SO High-State Output Voltage IOH = 1.0 mA
FS, SO Low-State Output Voltage
(16)
CIN
VCL(WAKE) VF(WAKE)
- 2.0 VSOH 0.8 VDD VSOL - ISO(LEAK) - 5.0 IUP 5.0 RFS - 6.0 15 40 TFEED 3.8 DTFEED -7.2
- 0.3 V - V 0.4 A 5.0 A 20 k
IOL = -1.6 mA SO Tri-State Leakage Current
CS > 0.7 VDD, 0Input Logic Pullup Current (17)
CS, VIN < 0.7 VDD
FSI Input pin External Pulldown Resistance (18) FSI Disabled, HS[0:3] state according to direct inputs state and SPI INx_SPI bits and A/O_s bit FSI Enabled, HS[0:3] OFF FSI Enabled, HS0 ON, HS[1:3] OFF FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF Temperature Feedback TA = 25C Temperature Feedback Derating
0 6.5 17 Infinite 3.9 -7.5
1.0 7.0 19 - V 4.0 -7.8 mV/C
Notes 13. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 14. 15. 16. 17. 18. No hysteresis on FSI and wake pins. Parameter is guaranteed by process monitoring but is not production tested. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. The current must be limited by a series resistance when using voltages > 7.0 V. Pullup current is with CS OPEN. CS has an active internal pullup to VDD. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the resistance value will always be within the desired (specified) range.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) Output Rising Slow Slew Rate A (DICR D3 = 0) (19) 9.0 V < VPWR < 16 V Output Rising Slow Slew Rate B (DICR D3 = 0) (20) 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate A (DICR D3 = 1) (19) 9.0 V < VPWR < 16 V Output Rising Fast Slew Rate B (DICR D3 = 1) (20) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate A (DICR D3 = 0) (19) 9.0 V < VPWR < 16 V Output Falling Slow Slew Rate B (DICR D3 = 0) (20) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate A (DICR D3 = 1) (19) 9.0 V < VPWR < 16 V Output Falling Fast Slew Rate B (DICR D3 = 1) (20) 9.0 V < VPWR < 16 V Output Turn-ON Delay Time in Slow Slew Rate (21) DICR = 0 Output Turn-ON Delay Time in Fast Slew Rate (21) DICR = 1 Output Turn-OFF Delay Time in Slow Slew Rate Mode (22) DICR = 0 Output Turn-OFF Delay Time in Fast Slew Rate Mode (22) DICR = 1 Overcurrent Low Detection Blanking Time OCLT[1:0]: 00 OCLT[1:0]: 01 (23) OCLT[1:0]: 10 OCLT[1:0]: 11 t DLY_FAST(ON) 1.0 6.0 200 50 155 - 75 0.15 100 s 40 20 800 s 400 ms 202 - 95 0.3 t DLY_SLOW(ON) 2.0 30 200 s SRFB_FAST 0.025 0.3 1.0 s SRFA_FAST 0.5 1.5 3.0 V/s SRFB_SLOW 0.015 0.05 0.15 V/s SRFA_SLOW 0.1 0.3 0.75 V/s SRRB_FAST 0.025 0.3 1.0 V/s SRRA_FAST 0.5 1.5 3.0 V/s SRRB_SLOW 0.015 0.05 0.15 V/s SRRA_SLOW 0.1 0.3 0.75 V/s V/s Symbol Min Typ Max Unit
t DLY_SLOW(OF
F)
t DLY_FAST(OFF)
t OCL0 t OCL1 t OCL2 t OCL3
108 - 55 0.08
Notes 19. Rise and Fall Slew Rates A measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR - 3.5 V (see Figure 4, page 12). These parameters are guaranteed by process monitoring. 20. Rise and Fall Slew Rates B measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR - 3.5 V (see Figure 4). These parameters are guaranteed by process monitoring. 21. Turn-ON delay time measured from rising edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output ON to VHS[0 : 3] = 0.5 V with RL = 5.0 resistive load. 22. 23. Turn-OFF delay time measured from falling edge of any signal (IN[0 : 3], SCLK, CS) that would turn the output OFF to VHS[0 : 3] = VPWR 0.5 V with RL = 5.0 resistive load. This logical bit is not defined. Do not use.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, - 40C TA 125C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued) Overcurrent High Detection Blanking Time
CS to CSNS Valid Time (24)
(25)
Symbol
Min
Typ
Max
Unit
tOCH t CNSVAL t WDTO0 t WDTO1 t WDTO2 t WDTO3
fPWM
1.0 - 446 223 1800 900 -
5.0 - 558 279 2250 1125 300
20 10 725 363 2925 1463 -
s s ms
Watchdog Timeout WD[1:0] : 00 WD[1:0] : 01 WD[1:0] : 10 WD[1:0] : 11
Direct Input Switching Frequency (DICR D3 = 0) SPI INTERFACE CHARACTERISTICS (RST, CS, SCLK, SI, SO) Maximum Frequency of SPI Operation Required Low State Duration for RST
(26)
Hz
f SPI t WRST t CS t ENBL t LEAD t WSCLKh t WSCLKl
(27) (27)
- - - - - - - - - - -
- 50 - - 50 - - 50 25 25 25 25 - - - 65 65
3.0 350 300 5.0 167 167 167 167 83 83 50
MHz ns ns s ns ns ns ns ns ns ns ns
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (27) Rising Edge of RST to Falling Edge of CS (Required Setup Time) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (27) Required High State Duration of SCLK (Required Setup Time)
(27)
Required Low State Duration of SCLK (Required Setup Time) (27) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) SI to Falling Edge of SCLK (Required Setup Time) (28) Falling Edge of SCLK to SI (Required Setup Time) SO Rise Time CL = 200 pF SO Fall Time CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (28) SI, CS, SCLK, Incoming Signal Fall Time (28) Time from Falling Edge of CS to SO Low Impedance
(29) (28)
t LAG t SI (SU) t SI (HOLD) t RSO t FSO
-
50 50 50 145 145 105 ns ns ns ns ns
t RSI t FSI t SO(EN) t SO(DIS) t VALID
- - - - -
Time from Rising Edge of CS to SO High Impedance (30) Time from Rising Edge of SCLK to SO Data Valid 0.2 VDD SO 0.8 VDD, CL = 200 pF
(31)
Notes 24. Time necessary for the CSNS to be with 5% of the targeted value. 25. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t WDTO is consistent for all configured watchdog timeouts. 26. RST low duration measured with outputs enabled and going to OFF or disabled condition. 27. Maximum setup time required for the 33874 is the minimum guaranteed time needed from the microcontroller. 28. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 29. Time required for output status data to be available for use at SO. 1.0 k on pullup on CS. 30. Time required for output status data to be terminated at SO. 1.0 k on pullup on CS. 31. Time required to obtain valid data out from SO following the rise of SCLK.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
CS
VPWR VPWR VPWR - 0.5V VPWR -0.5 V VPWR - V VPWR -3.53V
SRRB_SLOW & SRRB
SRFB_SLOW & SRFB_FAST SRFA_SLOW & SRFA_FAST
SRRA_SLOW & SRRA_FAST
0.5V V 0.5
t t DLY_SLOW(OFF) & t DLY_FAST(OFF)
tDLY(ON)
Figure 4. Output Slew Rate and Time Delays
IOCHx
Load Current
t OCH IOCLx t OCLx
Time Figure 5. Overcurrent Shutdown
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
IOCH0 IOCH1 IOCL0
IOCL1
Load Current
IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7
Time
t OCH t OCL3 t OCL2 t OCL0
Figure 6. Overcurrent Low and High Detection
VIH VIH
RSTB RST
0.2 VDD 0.2 VDD tWRST
TwRSTB tENBL TENBL TCSB t CS
VIL VIL
0.7 VDD 0.7VDD CS CSB 0.2 VDD 0.7VDD
VIH VIH VIL VIL
tTlead LEAD
t WSCLKh TwSCLKh
t RSI
TrSI
t LAG Tlag
VIH VIH VIL VIL
SCLK SCLK
0.7 VDD 0.7VDD 0.2 VDD
0.2VDD
t TSIsu SI(SU)
t WSCLKl TwSCLKl t SI(HOLD) TSI(hold)
tTfSI FSI
VIH VIH Valid Don't Care
SI SI
Don't Care
0.7 VDD 0.7 VDD 0.2VDD 0.2 VDD
Valid
Don't Care
VIH VIL
Figure 7. Input Timing Switching Characteristics
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
tRSI
TrSI TfSI
tFSI
3.5 3.5V V
VOH VOH 50% 1.0V 1.0 V VOL VOL
SCLK SCLK
t SO(EN)
TdlyLH
SO SO
0.7 VDD VDD
VOH VOH VOL VOL
0.2 VDD 0.2 VDD TrSO t RSO TVALID t VALID
Low-to-High Low to High
SO
SO
0.7 VDD High to Low High-to-Low 0.7 VDD
TfSO t FSO
VOH VOH
TdlyHL
t SO(DIS)
0.2VDD 0.2 VDD
VOL VOL
Figure 8. SCLK Waveform and Valid SO Data Delay Time
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33874 is one in a family of devices designed for lowvoltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (35 m) can control the high sides of four separate resistive or inductive loads. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for PWM control if desired. The 33874 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33874 is packaged in a power-enhanced 12 x 12 nonleaded PQFN package with exposed tabs.
FUNCTIONAL PIN DESCRIPTION
OUTPUT CURRENT MONITORING (CSNS)
The Current Sense pin sources a current proportional to the designated HS0 : HS3 output. That current is fed into a ground-referenced resistor and its voltage is monitored by an MCU's A/D. The output to be monitored is selected via the SPI. This pin can be tri-stated through SPI.
when transitioning from logic [0] to logic [1]. This pin should not be allowed to be logic [1] until VDD is in regulation. This pin has a passive internal pulldown.
CHIP SELECT (CS)
The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 33874 latches in data from the Input Shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an active internal pullup, IUP.
SERIAL INPUTS (IN0, IN1, IN2, IN3)
The IN0 : IN3 high-side input pins are used to directly control HS0 : HS3 high-side output pins, respectively. An SPI register determines if each input is activated or if the input logic state is OR ed or AND ed with the SPI instruction. These pins are to be driven with 5.0 V CMOS levels, and they have an active internal pulldown current source.
TEMPERATURE FEEDBACK (TEMP)
This pin reports an analog voltage value proportional to the temperature of the GND. It is used by the MCU to monitor board temperature.
SERIAL CLOCK (SCLK)
The SCLK pin clocks the internal shift registers of the 33874 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pulldown. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance) (see Figure 9, page 17).
FAULT STATUS (FS)
This pin is an open drain configured output requiring an external pullup resistor to VDD for fault reporting. If a device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin.
WAKE
This input pin controls the device mode and watchdog timeout feature if enabled. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has a passive internal pulldown.
SERIAL INPUT (SI)
This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 to D0. The internal registers of the 33874 are configured and controlled using a 5-bit addressing scheme described in Table 8, page 21. Register addressing and configuration are
RESET (RST)
This input pin is used to initialize the device configuration and fault registers, as well as place the device in a lowcurrent sleep mode. The pin also starts the watchdog timer
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described in Table 9, page 21. The SI input has an active internal pulldown, IDWN.
DIGITAL DRAIN VOLTAGE (VDD)
This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device.
the CS pin is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and input status descriptions are provided in Table 16, page 25.
HIGH-SIDE OUTPUTS (HS3, HS1, HS0, HS2)
Protected 35 m high-side power output pins to the load.
GROUND (GND)
This pin is the ground for the device.
FAIL-SAFE INPUT (FSI)
The value of the resistance connected between this pin and ground determines the state of the outputs after a Watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF or the output HSO only is ON. If the FSI pin is left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in the Fail-Safe state. When the FSI pin is connected to GND, the Watchdog circuit and Fail-Safe operation are disabled. This pin incorporates an active internal pullup current source.
POSITIVE POWER SUPPLY (VPWR)
This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package.
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until
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FUNCTIONAL DEVICE OPERATION
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CS). The SI / SO pins of the 33874 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels.
CSB CS
CS
SCLK
SI
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1 OD0
Notes 1. RST is a logic [1] state during the above operation. NOTES: 1. 2. D15:D0 relate state during therecent ordered entry of data into the device. RSTB is in a logic H to the most above operation. out of 2. 3. OD15:OD0 and D15to the firstmostbits ofordered entry of program data into the LUX IC the device. DO, D1, D2, ... , relate relate to the 16 recent ordered fault and status data device.
Figure 9. Single 16-Bit Word SPI Communication
OPERATIONAL MODES
The 33874 has four operating modes: Sleep, Normal, Fault, and Fail-Safe. Table 5 summarizes details contained in succeeding paragraphs. Table 5. Fail-Safe Operation and Transitions to Other 33874 Modes
Mode Sleep Normal Fault FS x 1 0 0 0 1 1 1 FailSafe Wake RST WDTO 0 x 1 1 0 0 1 1 0 1 1 0 1 1 1 0 Yes x No No Comments Device is in Sleep mode. All outputs are OFF Normal mode. Watchdog is active if enabled. Device is currently in fault mode. The faulted output(s) is (are) OFF. Watchdog has timed out and the device is in Fail-Safe Mode. The outputs are as configured with the RFS resistor connected to FSI. RST and WAKE must go from logic [1] to logic [0] simultaneously to bring the device out of the Fail-safe mode or momentarily tied the FSI pin to ground.
SLEEP MODE
The Default mode of the 33874 is the Sleep mode. This is the state of the device after first applying battery voltage (VPWR) prior to any I/O transitions. This is also the state of the device when the WAKE and RST are both logic [0]. In the Sleep mode, the output and all unused internal circuitry, such as the internal 5.0 V regulator, are off to minimize current draw. In addition, all SPI-configurable features of the device are as if set to logic [0]. The 33874 will transition to the Normal or Fail-Safe operating modes based on the WAKE and RST inputs as defined in Table 5.
NORMAL MODE
The 33874 is in Normal mode when: * VPWR and VDD are within the normal voltage range. * RST pin is logic [1]. * No fault has occurred.
FAIL-SAFE MODE FAIL-SAFE MODE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting
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resistance limiting the internal clamp current according to the specification. The Watchdog timeout is a multiple of an internal oscillator and is specified in the Table 15, page 23. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR, the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized. During the Fail-Safe mode, the outputs will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 6). Table 6. Output State During Fail-Safe Mode
RFS (k) 0 (shorted to ground) 6.0 15 30 (open) High-Side State Fail-Safe Mode Disabled All HS OFF HS0 ON HS1 : HS3 OFF HS0 and HS2 ON HS1 and HS3 OFF
Table 5 summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI pin is tied to GND, the Watchdog fail-safe operation is disabled.
LOSS OF VDD
If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The outputs can still be driven by the direct inputs IN0 : IN3. The 33874 uses the battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing fail-safe device operation with no VDD supplied. In this state, the watchdog, undervoltage, overvoltage, overtemperature (latched) and overcurrent circuitry are fully operational with default values.
FAULT MODE
This 33874 indicates the faults below as they occur by driving the FS pin to logic [0]: * * * * Overtemperature fault Overvoltage and undervoltage fault Open load fault Overcurrent fault (high and low)
In the Fail-Safe mode, the SPI register content is retained except for overcurrent high and low detection levels, timing and latched overtemperature which are reset to their default value (SOCL, SOCH, and OCTL and OT_latch_[0:3] bits). Then the watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value) are fully operational. The Fail-Safe mode can be detected by monitoring the WDTO bit D2 of the WD register. This bit is logic [1] when the device is in Fail-Safe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST pins from logic [1] to logic [0] or forcing the FSI pin to logic [0].
The FS pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, overtemperature (in case of latching configuration) and in some cases of undervoltage. The FS pin reports all faults. For latched faults, this pin is reset by a new Switch ON command (via SPI or direct input IN). Fault information is retained in the fault register and is available (and reset) via the SO pin during the first valid SPI communication (refer to Table 17, page 25).
PROTECTION AND DIAGNOSTIC FEATURES
OVERTEMPERATURE FAULT (LATCHING OR NON-LATCHING)
The 33874 incorporates overtemperature detection and shutdown circuitry for each output structure. The overtemperature is latched per default and can be unlatched through SPI with OT_latch_[0:3] bits. An overtemperature fault condition results in turning OFF the corresponding output. To remove the fault and be able to turn ON again the outputs, the failure must be removed and: * in Normal Mode: the corresponding output must be commanded OFF and ON again in case of overtemperature latched (OT_latch bit = 0). * in Normal Mode: the corresponding output turns ON automatically if the temperature is below TSD-TSD(HYS) in case of unlatched overtemperature (OT_latch bit = 1).
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* in Fail-Safe Mode: the FSI input must be grounded and then set to its nominal voltage to switch ON the outputs. The overtemperature fault (one for each output) is reported by SPI. If the overtemperature is latched, the SPI reports OTF_s = [1] and OCLF_s = [1]. In case of nonlatched, OTF_s = [1] only is reported. The fault bits will be cleared in the status register after either a valid SPI read command or a power on reset of the device.
OVERCURRENT FAULT (LATCHING)
The 33874 has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent
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detection levels, defined by IOCH and IOCL, are illustrated in Figure 6, page 13. The eight different overcurrent low detect levels (IOCL0 : IOCL7) are illustrated in Figure 6. If the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the output OFF. If at any time the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCH driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again.
UNDERVOLTAGE SHUTDOWN (LATCHING OR NON-LATCHING)
The output(s) will latch off at some battery voltage below 6.0 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. In the case where battery voltage drops below the undervoltage threshold (VPWRUV) output will turn off, FS will go to logic 0, and the fault register UVF bit will be set to 1. Two cases need to be considered when the battery level recovers : * If outputs command are low, FS will go to logic 1 but the UVF bit will remain set to 1 until the next read operation (warning report). * If the output command is ON, then FS will remain at logic 0. The output must be turned OFF and ON again to re-enable the state of output and release FS. The UVF bit will remain set to 1 until the next read operation. The undervoltage protection can be disabled through SPI (bit UV_dis = 1). In this case, the FS does not report any undervoltage fault condition, UVF bit is set to 1, and the output state is not changed as long as the battery voltage does not drop any lower than 2.5 V. The daisy chain feature is available under VDD in nominal conditions.
OVERVOLTAGE FAULT (NON-LATCHING)
The 33874 shuts down the output during an overvoltage fault (OVF) condition on the VPWR pin. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit D1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection can be disabled through SPI (bit OV_DIS). When disabled, the returned SO bit OD13 still reflects any overvoltage condition (overvoltage warning).
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Table 7. Device behavior in case of Undervoltage
Quad High-Side Switch (VPWR Battery Voltage) VPWR > VPWRUV UV Enable UV Enable UV Enable UV Enable IN[0:3]=0 IN[0:3]=0 IN_x***=1 IN_x***=1 (Falling VPWR) (Rising VPWR) (Falling VPWR) (Rising VPWR) OFF 1 0 OFF 1 1 until next read ON 1 0 OFF 0 1 UV Disable UV Disable IN[0:3]=0 IN_x***=1 (Falling or (Falling or Rising VPWR) Rising VPWR) OFF 1 0 (falling) 1 until next read (rising) OFF 1 1 OFF 1 ON 1 0 (falling) 1 until next read (rising) ON 1 1 ON 1
State
Output State FS State SPI Fault Register UVF Bit
VPWRUV > VPWR > UVPOR
Output State FS State SPI Fault Register UVF Bit
OFF 0 1 OFF 1
OFF 0 1 OFF 1
OFF 0 1 OFF 1
OFF 0 1 OFF 1
UVPOR > VPWR > 2.5 V
Output State FS State
SPI Fault Register 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read UVF Bit 2.5 V > VPWR > 0V Output State FS State OFF 1 OFF 1 OFF 1 OFF 1 OFF 1 OFF 1
SPI Fault Register 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read 1 until next read UVF Bit Comments UV fault is not latched UV fault is not latched UV fault is latched
= Typical value; not guaranteed = While VDD remains within specified range. *** = IN_x is equivalent to IN_x direct input or IN_spi_s SPI input.
OPEN LOAD FAULT (NON-LATCHING)
The 33874 incorporates open load detection circuitry on the output. Output open load fault (OLF) is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled through SPI (bit OL_DIS). It is recommended to disable open load
enhanced to keep the junction temperature less than 150C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required except on VDD.
GROUND DISCONNECT PROTECTION
In the event the 33874 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection. A 10K resistor needs to be added between the wake pin and the rest of the circuitry in order to ensure that the device turns off in case of ground disconnect and to prevent this pin to exceed its maximum ratings. Current limit resistors in the digital input lines protect the digital supply against excessive current (10k typical).
circuitry in case of a permanent disconnected load.
REVERSE BATTERY
The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output's gate is
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LOGIC COMMANDS AND REGISTERS
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending with the LSB, D0 (Table 8). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the MSB, D15, is the watchdog bit. In some cases, output selection is done with bits D12 : D11. The next three bits, D10 : D8, are used to select the command register. The remaining five bits,
D4 : D0, are used to configure and control the outputs and their protection features. Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 33874 has defined registers, which are used to configure the device and to control the state of the outputs. Table 9, page 21, summarizes the SI registers.
Table 8. SI Message Bit Assignment
Bit Sig MSB SI Msg Bit D15 D14 : D15 D12 : D11 D10 : D8 D7 : D5 D4 : D1 LSB D0 Message Bit Description Watchdog in: toggled to satisfy watchdog requirements. Not used. Register address bits used in some cases for output selection. Register address bits. Not used. Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content.
Table 9. Serial Input Address and Configuration Bit Map
SI Data SI Register D15 STATR_s OCR0 OCR1 WDIN WDIN WDIN D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 A1 A1 0 0 0 X 0 0 1 A0 A0 A0 0 1 0 X 0 0 0 0 0 1 1 1 1 X 0 0 0 1 1 0 0 0 1 X D8 D7 D6 D5 0 1 1 0 1 0 1 1 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 SOA4 0 0 0 0 0 0 0 0 0 0 D3 SOA3 IN3_SPI CSNS3 EN SOCH_s OL_DIS_s FAST_SR_s OT_latch-1 OT_latch_3 D2 SOA2 IN2_SPI CSNS2 EN SOCL2_s OCL_DIS_s D1 SOA1 IN1_SPI CSNS1 EN SOCL1_s OCLT1_s D0 SOA0 IN0_SPI CSNS0 EN SOCL0_s OCLT0_s A/O_s OV_DIS WD0
SOCHLR_s WDIN CDTOLR_s WDIN DICR_s UOVR WDR NAR RESET WDIN WDIN WDIN WDIN 0
CSNS_high_s DIR_DIS_s OT_latch_0 OT_latch_2 UV_DIS WD1
No Action (Allow Toggling of D15- WDIN) 0 0 0
x = Don't care. s = Output selection with the bits A1A0 as defined in Table 10. D15 is used to toggle watchdog event (WDIN)
DEVICE REGISTER ADDRESSING
The following section describes the possible register addresses and their impact on device operation.
ADDRESS 00000 -- STATUS REGISTER (STATR_S)
The STATR register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to the device status, this feature provides the ability to read the content of the OCR0, OCR1, SOCHLR,
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CDTOLR, DICR, UOVR, WDR, and NAR registers. (Refer to the section entitled Serial Output Communication (Device Status Return Data) beginning on page 23.)
Table 11. Overcurrent Low Detection Levels
SOCL2_s* SOCL1_s* SOCL0_s* (D2) (D1) (D0) Overcurrent Low Detection (Amperes) HS0 to HS3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 10 8.9 7.9 7.0 5.8 4.8 3.9 2.8
ADDRESS 00001-- OUTPUT CONTROL REGISTER (OCR0)
The OCR0 register allows the MCU to control the ON / OFF state of four outputs through the SPI. Incoming message bit D3 : D0 reflects the desired states of the four high-side outputs (INx_SPI), respectively. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF.
ADDRESS 01001-- OUTPUT CONTROL REGISTER (OCR1)
Incoming message bits D3 : D0 reflect the desired output that will be mirrored on the Current Sense (CSNS) pin. A logic [1] on message bits D3 : D0 enables the CSNS pin for outputs HS3 : HS0, respectively. In the event the current sense is enabled for multiple outputs, the current will be summed. In the event that bits D3 : D0 are all logic [0], the output CSNS will be tri-stated. This is useful when several CSNS pins of several devices share the same A /D converter.
* "_s" refers to the output, which is selected through bits D12 : D11;
refer to Table 10, page 22.
Table 12. Overcurrent High Detection Levels
Overcurrent High Detection (Amperes) SOCH_s* (D3) HS0 to HS3 0 1 refer to Table 10, page 22. 55 40
ADDRESS A1A0010 -- SELECT OVERCURRENT HIGH AND LOW REGISTER (SOCHLR_S)
The SOCHLR_s register allows the MCU to configure the output overcurrent low and high detection levels, respectively. Each output "s" is independently selected for configuration based on the state of the D12 : D11 bits (Table 10). Table 10. Output Selection
A1 (D12) 0 0 1 1 A0 (D11) 0 1 0 1 HS_s HS0 HS1 HS2 HS3
* "_s" refers to the output, which is selected through bits D12 : D11;
ADDRESS A1A0011 -- CURRENT DETECTION TIME AND OPEN LOAD REGISTER (CDTOLR)
The CDTOLR register is used by the MCU to determine the amount of time the device will allow an overcurrent low condition before an output latches OFF. Each output is independently selected for configuration based on A1A0 , which are the state of the D12 : D11 bits (refer to Table 10, page 22). Bits D1 : D0 (OCLT1_s : OCLT0_s) allow the MCU to select one of three overcurrent fault blanking times defined in Table 13. Note that these timeouts apply only to the overcurrent low detection levels. If the selected overcurrent high level is reached, the device will latch off within 20 s. Table 13. Overcurrent Low Detection Blanking Time
OCLT[1:0]_s* 00 01 10 11 refer to Table 10, page 22. Timing 155 ms Do not use 75 ms 150 s
Each output can be configured to different levels. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements matching system characteristics. Bits D2 : D0 set the overcurrent low detection level to one of eight possible levels, as shown in Table 11, page 22. Bit D3 sets the overcurrent high detection level to one of two levels, as outlined in Table 12, page 22.
* "_s" refers to the output, which is selected through bits D12 : D11;
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A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent low detection feature. When disabled, there is no timeout for the selected output and the overcurrent low detection feature is disabled. A logic [1] on bit D3 (OL_DIS_s) disables the open load (OL) detection feature for the output corresponding to the state of bits D12 : D11.
ADDRESS 00101 -- UNDERVOLTAGE / OVERVOLTAGE AND HS[0,1] OVERTEMPERATURE REGISTER (UOVR)
The UOVR register disables the undervoltage (D1) and/or overvoltage (D0) protection. When these two bits are [0], the under- and overvoltage are active (default value). The UOVR register allows the overtemperature detection latching on the HS0 and HS1. To latch the overtemperature, the bits (OT_latch_1 and OT_latch_0) must be set to [0] which is the default value. To disable the latching, both bits must be set to [1].
ADDRESS A1A0100 -- DIRECT INPUT CONTROL REGISTER (DICR)
The DICR register is used by the MCU to enable, disable, or configure the direct IN pin control of each output. Each output is independently selected for configuration based on the state bits D12 : D11 (refer to Table 10, page 22). For the selected output, a logic [0] on bit D1 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D1 will disable the output from direct control. While addressing this register, if the Input was enabled for direct control, a logic [1] for the D0 (A/O_s) bit will result in a Boolean AND of the IN pin with its corresponding IN_SPI D[4:0] message bit when addressing OCR0. Similarly, a logic [0] on the D0 pin results in a Boolean OR of the IN pin to the corresponding message bits when addressing the OCR0. This register is especially useful if several loads are required to be independently PWM controlled. For example, the IN pins of several devices can be configured to operate all of the outputs with one PWM output from the MCU. If each output is then configured to be Boolean ANDed to its respective IN pin, each output can be individually turned OFF by SPI while controlling all of the outputs, commanded on with the single PWM output. A logic [1] on bit D2 (CSNS_high_s) is used to select the high ratio on the CSNS pin for the selected output. The default value [0] is used to select the low ratio (Table 14). Table 14. Current Sense Ratio
Current Sense Ratio CSNS_high_s* (D2) HS0 to HS3 0 1 1/7200 1/21400
ADDRESS 01101 -- WATCHDOG AND HS[2,3] OVERTEMPERATURE REGISTER (WDR)
The WDR register is used by the MCU to configure the Watchdog timeout. The Watchdog timeout is configured using bits D1 and D0. When D1 and D0 bits are programmed for the desired watchdog timeout period (Table 15), the WDSPI bit should be toggled as well, ensuring the new timeout period is programmed at the beginning of a new count sequence. The WDR register allows the overtemperature detection latching on the HS2 and HS3. To latch the overtemperature, the bits (OT_latch_3 and OT_latch_2) must be set to [0] which is the default value. To disable the latching, both bits must be set to [1]. Table 15. Watchdog Timeout
WD[1:0] (D1, D0) 00 01 10 11 Timing (ms) 558 279 2250 1125
ADDRESS 00110 -- NO ACTION REGISTER (NAR)
The NAR register can be used to no-operation fill SPI data packets in a daisy-chain SPI configuration. This would allow devices to be unaffected by commands being clocked over a daisy-chained SPI configuration. By toggling the WD bit (D15) the watchdog circuitry would continue to be reset while no programming or data read back functions are being requested from the device.
* "_s" refers to the output, which is selected through bits D12 : D11; refer to Table 10, page 22.
A logic [1] on bit D3 (FAST_SR_s) is used to select the high speed slew rate for the selected output, the default value [0] corresponds to the low speed slew rate.
SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA)
When the CS pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new message data is clocked into the SI pin. The first sixteen bits of data clocking out of the SO, and following a CS transition, is dependent upon the previously written SPI word.
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Any bits clocked out of the Serial Output (SO) pin after the first 16 bits will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as message verification. A valid message length is determined following a CS transition of [0] to [1]. If there is a valid message length, the data is latched into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3, OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the registers which are output specific; viz., Fault, SOCHLR, CDTOLR, and DICR registers. Note that the SO data will continue to reflect the information for each output (depending on the previous OD4, OD3 state) that was selected during the most recent STATR write until changed with an updated STATR write. The output status register correctly reflects the status of the STATR-selected register data at the time that the CS is pulled to a logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exceptions: * The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred.
* Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored. * The RST pin transition from a logic [0] to [1] while the WAKE pin is at logic [0] may result in incorrect data loaded into the Status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored.
SERIAL OUTPUT BIT ASSIGNMENT
The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 16, page 25, summarizes SO returned data for bits OD15 : OD0. * Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message. * Bit OD14 remains logic [0] except when an undervoltage condition occurred. * Bit OD13 remains logic [0] except when an overvoltage condition occurred. * Bits OD12 : OD8 reflect the state of the bits SOA4 : SOA0 from the previously clocked in message. * Bits OD7 : OD4 give the fault status flag of the outputs HS3 : HS0, respectively. * The contents of bits OD3 : OD0 depend on bits D4 : D0 from the most recent STATR command SOA4 : SOA0 as explained in the paragraphs following Table 16.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 16. Serial Output Bit Map Description
Previous STATR SO SO SO SO SO OD A4 A3 A2 A1 A0 15
START A1 A0 _s OCR0 OCR1 0 0 0 1 0 0 0 0 0 0 0 1
SO Returned Data OD 14 OD 13 OD 12 OD 11 OD OD9 OD8 OD7 OD6 OD5 OD4 10
ST2 ST2 ST2 ST2 ST1 ST1 ST1 ST1 ST0 ST0 ST0 ST0
OD3
OD2
OD1
OD0
0 WDIN UVF 1 WDIN UVF 1 WDIN UVF 0 WDIN UVF
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3
OTF_s IN3_SPI CSNS3 EN SOCH_s
OCHF_s IN2_SPI CSNS2 EN SOCL2_s
OCLF_s IN1_SPI
OLF_s IN0_SPI
CSNS1 EN CSNS0 EN SOCL1_s SOCL0_s
SOCHL A1 A0 R_s CDTOL A1 A0 R_s DICR_s A1 A0 UOVR WDR PINR0 PINR1 PINR2 0 0 0 0 0 0 1 0 1 1
0 1 1 1 1 1 1
1 0 0 0 1 1 1
1 WDIN UVF 0 WDIN UVF 1 WDIN UVF 1 WDIN UVF 0 WDIN UVF 0 WDIN UVF 1 WDIN UVF 0 0
OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 OVF SOA4 SOA3 SOA2 SOA1 SOA0 ST3 0 0 0 0 0 0 0
ST2 ST2 ST2 ST2 ST2 ST2 ST2 0
ST1 ST1 ST1 ST1 ST1 ST1 ST1 0
ST0 ST0
OL_DIS_s
OCL_DIS_s
OCLT1_s OCLT0_s A/O_s OV_DIS WD0 WAKE IN0 X 0
Fast_SR_s CSNS_high_s DIR_DIS_s UV_DIS WD1 WD_en IN1 X 0
ST0 OT_latch_1 OT_latch_0 ST0 0 WDTO
ST0 HS2_failsafe HS0_failsafe ST0 IN3 IN2
ST0 OT_latch_3 OT_latch_2 0 0 0
RESET N/A N/A N/A N/A N/A
s = Output selection with the bits A1A0 as defined in Table 10, page 22. ID[1,0]: product identification
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0000
Bits OD3 : OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits A1A0 (Table 17). Table 17. Output-Specific Fault Register
OD3 OTF_s OD2 OCHF_s OD1 OCLF_s OD0 OLF_s
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0010
Data returned in bits OD3 : OD0 are programmed current values for the overcurrent high detection level (refer to Table 12, page 22) and the overcurrent low detection level (refer to Table 11, page 22), corresponding to the output previously selected with A1A0.
PREVIOUS ADDRESS SOA4 : SOA0= A1A0011
The returned data contains the programmed values in the CDTOLR register for the output selected with A1A0.
s = Selection of the output.
Note The FS pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (via SPI or direct input IN).
PREVIOUS ADDRESS SOA4 : SOA0 = A1A0100
The returned data contains the programmed values in the DICR register for the output selected with A1A0.
PREVIOUS ADDRESS SOA4 : SOA0 = 00001
Data in bits OD3 : OD0 contains IN3_SPI : IN0_SPI programmed bits for outputs HS3 : HS0, respectively.
PREVIOUS ADDRESS SOA4 : SOA0 = 00101
The returned data contains the programmed values in the UOVR register.
PREVIOUS ADDRESS SOA4 : SOA0 = 01001
Data in bits OD3 : OD0 contains the programmed CSNS3 EN : CSNS0 EN bits for outputs HS3 : HS0, respectively.
PREVIOUS ADDRESS SOA4 : SOA0 = 01101
The returned data contains the programmed values in the WDR register. Bit OD2 (WDTO) reflects the status of the
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
watchdog circuitry. If WDTO bit is logic [1], the watchdog has timed out and the device is in Fail-Safe mode. IF WDTO is logic [0], the device is in Normal mode (assuming the device is powered and not in the Sleep mode), with the watchdog either enabled or disabled.
placed at the FSI pin. OD1 indicates if the watchdog is enabled or not. OD0 returns the state of the WAKE pin.
PREVIOUS ADDRESS SOA4 : SOA0 = 01110
The returned data OD3 : OD0 reflects the state of the direct pins IN3 : IN0, respectively.
PREVIOUS ADDRESS SOA4 : SOA0 = 00110
The returned data OD3 and OD2 contain the state of the outputs HS2 and HS0, respectively, in case of Fail-Safe state. This information is stated with the external resistance
PREVIOUS ADDRESS SOA4 : SOA0 = 01111
The returned data OD3 -OD2 reports the overtemperature bits configuration of the outputs [3, 2] set through the WDR SPI register.
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PACKAGING SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
The 33874 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The 33874 was qualified in accordance with JEDEC standards JESD22-A113-B and J-STD-020A. The recommended reflow conditions are as follows: * Convection: 235C +5 .0/ -0C * Vapor Phase Reflow (VPR): 235C +5.0 / -0C * Infrared (IR) / Convection: 235C +5.0 / -0C The maximum peak temperature during the soldering process should not exceed 240C. The time at maximum temperature should range from 10 s to 40 s maximum.
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARL10596D listed below. PNA SUFFIX (PB-FREE) 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D ISSUE C
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TYPICAL APPLICATION INTRODUCTION
TYPICAL APPLICATION
INTRODUCTION
The 33874 can be configured in several applications. The figure below shows the 33874 in a typical lighting application.
VPWR VDD
Voltage regulator
VDD VDD VDD 10k VDD I/O I/O I/O I/O I/O SCLK CS I/O SO SI A/D A/D 1k R1 10k 10k 10k 10k 10k 10k 10k 10k 10k 100nF 10F NC WAKE FS IN0 IN1 IN2 IN3 SCLK CS RST SI SO TEMP CSNS FSI 33874
HS0 VPWR
VPWR
VDD
VPWR
100nF
LOAD 0
21W
HS1
5W
Microcontroller
LOAD 1
21W
HS2
5W
LOAD 2
21W
HS3
5W
GND
LOAD 3
21W
5W
Automotive lamps do not tolerate high voltages very well. Tests of a few lamps indicate that failures can occur when 18V is applied for a few seconds. Consequently, PWM switching reduces the effective RMS voltage in order to drive bulbs safety. For example, to maintain the power dissipation associated with a 13V battery at 100% duty cycle, the duty cycle would be adjusted to (13/18), or 52%, when the battery is at 18V. The loads must be chosen in order to guarantee the device normal operating condition as junction temperature from -40 to 150 C. In case of permanent short-circuit conditions, the duration and number of activation cycles must be limited with a dedicated MCU fault management using the fault reporting through SPI.
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TYPICAL APPLICATION
STANDALONE MODE
This section consists of evaluating the MC33874 standalone capability. All protection functions are available without SPI communication. Nevertheless, any configuration is possible without an MCU to communicate by SPI. Some functions still enable, but diagnosis is reduced. Available functions and default parameters are detailed next.
CONFIGURATION WITHOUT MCU
The standalone mode is intended for customers who desire to plug the device and then immediately "play" with it, without having to connect it to a microcontroller. It also provides an easy way to evaluate the main electrical features. Without the Microcontroller to select programmable parameters and get full diagnosis via the SPI, the MC33874 runs with all parameters set to default. The input SPI pins and VDD must be connected to ground. Fail safe mode and watchdog timeout must be disabled by connecting the FSI to GND.
FUNCTIONING WITHOUT MCU
Without an MCU, SPI communication is not possible. Fail safe mode and watchdog timeout are not useful functions without an MCU, but still enable. Wake/Sleep mode is used to minimize current consumption during sleep mode. IN pins control the corresponding outputs and FS output is active (at 0 V) when a default occurs. The tables 1 and 2 illustrate the available functions without SPI and default parameters.
Table 1. Available Functions
Function Wake/Sleep mode Output ON/OFF control Over temperature protection Over voltage protection Under voltage protection Over current protection Open load, battery disconnect, reverse battery, ground disconnect protections Fault diagnosis Current sense Watchdog timeout Configurable slew rate Analog temperature feedback Available Via SPI or IN pin Available, can be unlatched Available, can be disabled Available, can be disabled Available, configurable (with 8 low levels and 2 high levels), can be disabled Available Full diagnosis with report by SPI and fault status pin (/FS) Available, 2 configurable ratios Available, 4 configurable timings 2 slew rate modes Available With SPI Available Only with IN pin Available Available, always enable Available, always enable Available, always enable with default values Available Limited fault diagnosis with Fault status pin only Not available Available, default value Default slew rate mode Available Without SPI
Table 2. Default SPI-configurable parameters
Configulable parameter Over voltage protection Under voltage protection Over current protection Over current low level Over current high level Over current detect blanking time Current sense Watchdog time timeout Slew rate mode Default typical value Enable Enable Enable OCLO0 OCHI0 tOCLO0 Disable TWDTO0 Slow mode
Table 2 illustrates default parameters after resetting or applying supply voltage to the MC33874. Levels and timings are typical values.
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TYPICAL APPLICATION
DIAGNOSIS WITHOUT MCU
When any fault appears (over current, open load...), a full diagnosis can be reported via the SPI. Without an MCU, the
fault status pin allows reduced diagnosis, as illustrated in table 3.
Table 3. Diagnosis without SPI
IN[x] level Normal operation H L L H L H L H L H L H L H HS[x] level H L L L L L L L L L H H Z H FS level H H L L L L H L H L L H L H Latched N/A
Over temperature
YES
Under voltage
YES
Over voltage
NO
Over current
YES
Short circuit to VPWR
NO
Open load
NO
H : High Level, L : Low Level, Z : High impedance, potential depends on the external circuit
We can note that it is not possible to distinguish over temperature, over current, under voltage, and over voltage. Nevertheless, Open load and short circuit to VPWR fault can be singled out. All protections are reported to Fault status pin (FS), Open load and short circuit to VPWR are reported only if the Output is OFF. If the fault is latched, the output must be turned OFF then ON to disable the fault.
CONCLUSION
Although the MC33874 is not fully functional without a microcontroller to control and program it, standalone functioning is safe because all protections are available. Diagnosis is limited, but the fault status pin will report any malfunction. This is a good way to evaluate the main electrical MC33874 features. Some simplified applications can also use the MC33874 switch without an MCU to drive a high power load with full protection.
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TYPICAL APPLICATION
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TYPICAL APPLICATION
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction This thermal addendum is provided as a supplement to the 33874 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. Packaging and Thermal Considerations This package is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2 RJA11 RJA12 RJA21 RJA22
.
33874
HIGH-SIDE SWITCH
PNA SUFFIX 98ARL10596D 24-PIN PQFN (12 x 12) Note For package dimensions, refer to the 33874 data sheet.
=
P1 P2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Table 18. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [C/W] Thermal Resistance RJAmn (1), (2) RJBmn (2), (3) RJAmn (1), (4) RJCmn (5) m = 1, n=1 20 6 53 <0.5 m = 1, n = 2 m = 2, n = 1 16 2.0 40 0.0 m = 2, n=2 1.0 39 26 73 1.0 0.2 0.2 1.0
Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, "infinite" heat sink attached to exposed pad.
Figure 10. Testboard According to JEDEC
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
Transparent Top View WAKE TEMP CSNS SCLK VDD
76.2 mm
RST
IN3
IN2
IN1 3
13 12 11 10 SO GND 16 17
9
8
7
6
5
4
IN0 2
CS
FS
SI
1 24 FSI GND
14 GND
23
HS3
18
22
HS2
A= 300sqmm
15 VPWR
A= 300sqmm
19 HS1
20 NC
21 HS0
MC33874 Pin Connections
24-Pin PQFN (12 x 12) 0.9 mm Pitch 12.0 mm x 12.0 mm Body
Figure 11. Thermal Test Board Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 19. Thermal Resistance Performance
1 = Power Chip, 2 = Logic Chip (C/W) Thermal Resistance Area A (mm2) 0 RJAmn 300 600 m = 1, n=1 53 44 42 m = 1, n = 2 m = 2, n = 1 38 32 30 m = 2, n=2 61 56 55
Outline:
Area A: Ambient Conditions:
RJA is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed.
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114.3 mm
ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
65 60 55 50 45 40 35 30 25 0 100 200
RJA11 RJA11
300
RJA12= RJA21 RJA12=RJA21
400
RJA22 RJA22
500
600
Figure 12. Steady State Thermal Resistance1 W step response; device on 1s thermal test board with heat spreading areas sq 600 mm.
100
10
1
0.1 1.00E-06
1.00E-04
1.00E-02
1.00E+00
1.00E+02
1.00E+04
RJA11 Series1
RJA12= Series2RJA21
RJA22 Series3
Figure 13. Transient Thermal Resistance
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REVISION HISTORY
REVISION HISTORY
Revision 3.0 4.0
Date 03/2006 04/2006
Description of Changes * * * * * * * * Implemented Revision History page Converted to Freescale format Added ROHS logo Added "It is recommended to disable open load circuitry in case of a permanent disconnected load."to the Open Load Fault (Non-Latching) paragraph Changed 1k to 10k in the second paragraph of Ground Disconnect Protection Added the section StandAlone mode to Typical Application Updated Package Dimensions to Issue C Added Thermal Addendum (Rev 2.0) to Data Sheet Corrected part number ordering information Modified Output Turn ON Delay Times on page 10 Changed status from Preliminary to Advance. Made changes the resistive loads on the Typical Applications diagram and added a paragraph describing the behavior of automotive lamps. Added new thermal curves to the Thermal Addendum (Rev 2.0) on page 33 Made updates to Thermal Resistance Performance on page 34 Made changes to Thermal Addendum (Rev 2.0) relating to Figure 11, Table 19, Thermal Resistance Performance, Figure 12, and Figure 13 Added Direct Input Switching Frequency to Dynamic Electrical Characteristics Table
5.0 6.0
6/2002 9/2006
* * * * * *
7.0 8.0
9/2006 4/2007
* *
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MC33874 Rev. 8.0 4/2007

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